PIC24FJ128GA008-I/PT【PDF 26/258 页】IC PIC MCU FLASH 128K 80TQFP

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3841

22页 23页 24页 25页 [26页]27页 28页 29页 30页

2005-2012 Microchip Technology Inc.

DS39747F-page 121

PIC24FJ128GA010 FAMILY

14.0

OUTPUT COMPARE

14.1

MODES OF OPERATION

Each output compare module has the following modes

of operation:

Single Compare Match mode

Dual Compare Match mode generating:

- Single Output Pulse mode

- Continuous Output Pulse mode

Simple Pulse-Width Modulation mode:

- with Fault protection input

- without Fault protection input

14.2

Setup for Single Output Pulse

Generation

When the OCM control bits (OCxCON<2:0>) are set to

‘100’, the selected output compare channel initializes

the OCx pin to the low state and generates a single

output pulse.

FIGURE 14-1:

OUTPUT COMPARE MODULE BLOCK DIAGRAM

Note:

This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. Refer to Section 16. “Output

Compare”

(DS39706) in the “PIC24F

Family

Reference

Manual”

for more

information.

Comparator

Output

Logic

OCM<2:0>

Output Enable

OCx(1)

Set Flag bit

OCxIF(1)

OCxRS(1)

Mode Select

Note 1:

Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels, 1

through 5.

OCFA pin controls OC1-OC4 channels; OCFB pin controls OC5.

Each output compare channel can use either Timer2 or Timer3.

OCTSEL

OCFA or OCFB(2)

TMR Register Inputs

from Time Bases

(see Note 3)

Period Match Signals

from Time Bases

(see Note 3)

OCxR(1)

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式